1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory module. More particularly, embodiments of the present invention relate to a semiconductor memory module including a module substrate having an asymmetrically aligned semiconductor memory chip mounted on the module substrate.
2. Description of the Related Art
A semiconductor memory module is generally manufactured by processes including a process for forming a semiconductor memory chip including integrated circuits on a semiconductor substrate, an electrical die sorting (EDS) process for inspecting and sorting the semiconductor memory chip, a package process for protecting the semiconductor memory chip, and a mounting process for installing the packaged semiconductor memory chip on a module substrate.
Semiconductor memory modules are developed to have a high degree of integration and a high degree of performance. Thus, the package process becomes more important to ensure these high degrees of integration and performance of the semiconductor memory modules because the package process may have substantial effect on various characteristics of the semiconductor memory module affecting the integration and performance, such as size, price, heat dissipation capacity, electrical conductance, reliability, etc.
Conventional semiconductor memory modules are generally manufactured by one of the following processes: a single inline package (SIP) process, a dual inline package (DIP) process, a quad flat package (QFT) process, or a ball grid array (BGA) process. However, other processes have been developed to ensure high degrees of integration for the semiconductor memory module, such as a chip scale package (CSP) process, a multi chip package (MCP) process, a stacked chip scale package (SCSP) process, or a wafer level chip scale package (WLCSP) process. Additionally, a wafer level package (WLP) process has been developed to improve the integration degree of the semiconductor memory module. In the WLP process, a series of processes, such as a die bonding process, a molding process, a trimming process, and a marking process are performed on semiconductor memory chips after forming the semiconductor memory chips on a wafer. Typically, the wafer is then cut to further the manufacturing process of the semiconductor memory module.
Semiconductor memory modules are usually divided into single inline memory modules and dual inline memory modules in accordance with an array of semiconductor memory chips thereof. Recently, the dual inline memory module ensuring high degrees of integration and capacity has become more widely used in various apparatuses because the semiconductor memory chips are mounted on both sides of the dual inline memory module. Additionally, the dimensions of semiconductor memory modules have been internationally standardized. For example, the dimensions of a semiconductor memory module employed in a general computer are different from those of a semiconductor memory module used in a notebook computer.
FIG. 1 is a plan view illustrating a conventional semiconductor memory module employed in a notebook computer, and FIG. 2 is a cross-sectional view illustrating the conventional semiconductor memory module shown in FIG. 1 taken along a line of I-I′.
Referring to FIGS. 1 and 2, a conventional semiconductor memory module 20 includes a module substrate 10, semiconductor memory chips 12, passive devices 14, and a filling member 18.
The module substrate 10 includes stacked integrated circuit substrates and a connector pin 11 disposed on one end portion of the module substrate 10. Each of the integrated circuit substrates has a size of about 67.6 mm×about 30.0 mm. Additionally, each of the semiconductor memory chips 12 has a size of about 14.0 mm×about 9.5 mm. Generally, eight semiconductor memory chips 12 arranged along two rows are mounted on the module substrate 10. The semiconductor memory chips 12 are mounted on the module substrate 10 using solder balls 13.
The passive devices 14 are typically arranged between the two rows of semiconductor memory chips 12. The filling member 18 is disposed between the module substrate 10 and the semiconductor memory chips 12 to enclose the solder balls 13. The filling member 18 generally includes a thermosetting resin. When a process is performed to evaluate the reliability of the semiconductor memory chips 12 mounted on the module substrate 10, the filling member 18 may prevent a connection failure between the module substrate 10 and the semiconductor memory chips 12 caused by the thermal expansion coefficient difference between the module substrate 10 and the semiconductor memory chips 12.
In these conventional semiconductor memory modules 20 used in a notebook computer, the semiconductor memory chips 12 occupy a large area of the module substrate 10 as shown in FIG. 1 such that the intervals between the semiconductor memory chips 12 become exceedingly small. However, as the intervals between the semiconductor memory chips 12 become small, the filling member 18 may not completely fill up the space between the module substrate 10 and the semiconductor memory chips 12. That is, the space between the module substrate 10 and the semiconductor memory chips 12 becomes so small that the filling member 1 8 may not easily fill up the space even though the filling member 18 may be applied when it is in a liquid phase. As a result, a void 15 may be generated in the space between the module substrate 10 and the semiconductor memory chips 12 as shown in FIG. 2 because the filling member 18 may not completely fill up the space between the module substrate 10 and the semiconductor memory chips 12. When the void 15 occurs in the space typically replete with the filling member 18, cracks in the solder balls 13 may be caused in a subsequent thermal process for combining the module substrate 10 and the semiconductor memory chips 12. This in turn, may cause an electrically failure as the module substrate 10 may not be electrically connected to the semiconductor memory chips 12. Thus, the semiconductor memory module may be faulty leading to reduced performance of both the semiconductor memory module and the notebook computer including the semiconductor memory module 20.